C. Papadopoulos, Th. Antonakopoulos and V. Makios:

The Medium Access Controller of a Customer Premises Network

The Asia-Pacific Conference on Communications - APCC '93, Taejon, Korea, August 1993, pp. 3C.4.1–3C.4.5.

Abstract:  This paper presents the architecture of an ATM controller for a Customer Premises Network (CPN). The controller has been designed to implement the cell assembly disassembly following the B-ISDN ATM layer functionality and the specific requirements of the medium access protocol used in the Buffer Insertion Cell-based LAN. The controller has been implemented using a commercially available FPGA and operates with a 25-MHz clock. The controller’s architecture has been based on five operational modules integrated in a single chip and its processing capability is 1.88 Mcell/sec. That makes the controller appropriate for use in high-speed applications, like in ATMALANs, CPNs in business and factory environments etc.

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