Sub-block Wear-leveling for NAND Flash

The Non-Volatile Memories Workshop (NVMW2011), San Diego, CA, March 6-8, 2011.

Abstract: In NAND Flash memories, the introduction of multi-level cells and the scaling to smaller cell structures has led to a significant decrease in endurance. Today, devices built in 20nm technology are typically specified for only 3K program/erase cycles. Using all cells to their limit is therefore of utmost importance. Strong error-correction codes are used to extend endurance. However, existing Flash management schemes retire an entire block when the first page hits its lifetime limit while other pages in the same block might still be used. We propose new wear-leveling schemes that can be used in addition to ECC to substantially extend the lifetime of Flash memories.

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